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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com product specification ps021410-0605 crimzon tm zlr16300 z8 low voltage rom mcus with infrared timers
disclaimer ps021410-0605 this publication is subject to replacement by a la ter edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com zilog is a registered trademark of zilog inc. in the unit ed states and in other countri es. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ?2005 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible us es and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not a ssume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devi ces sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose. e xcept with the express writt en approval of zilog, use of information, devices, or technology as critical components of life support syst ems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
crimzon tm zlr16300 product specification ps021410-0605 iii revision history each instance in table 1 reflects a change to this document from its previous revi- sion. to see more detail, click the appropriate link in the table. table 1. revision history of this document date revision level description page# december 2004 07 changed low power consumption and current usage for stop and halt modes, removed mask option note, and added characterization data to table 7. 1, 2, 8 removed preliminary designation all january 2005 08 changed low power consumption value to 5mw. changed stop and halt mode current values to 1.3 a and 0.5ma respectively. changed v cc low voltage protection typical rating to 1.8v. 1, 12 april 2005 09 clarified port 1 reserved address status by removing port 1 in figure 1 and adding a note in figure 12. reference cr5843. 3, 21 june 2005 10 added 1k and 2k parts. all
crimzon tm zlr16300 product specification ps021410-0605 table of contents iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 xtal1 crystal 1 (time-based input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 xtal2 crystal 2 (time-based output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 port 0 (p07?p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 port 2 (p27?p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 port 3 (p37?p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 expanded register file control registers (0d) . . . . . . . . . . . . . . . . . . . . . . . . 58 expanded register file control registers (0f) . . . . . . . . . . . . . . . . . . . . . . . . . 63 standard control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
crimzon tm zlr16300 product specification ps021410-0605 list of figures v list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. counter/timers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 20-pin dip/soic/ssop pi n configuration . . . . . . . . . . . . . . . . . . . . 5 figure 4. 28-pin dip/soic/ssop pi n configuration . . . . . . . . . . . . . . . . . . . . 6 figure 5. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. port 3 counter/timer output configuration . . . . . . . . . . . . . . . . . . . 17 figure 11. program memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. expanded register file architecture . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. register pointer?detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. glitch filter circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. transmit mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. 8-bit counter/timer circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. t8_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. t8_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. demodulation mode count capture flowchart . . . . . . . . . . . . . . . . 37 figure 21. demodulation mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. 16-bit counter/timer circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23. t16_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24. t16_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25. ping-pong mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 26. output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 28. oscillator confi guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 29. port configuration register (pcon) (write only) . . . . . . . . . . . . . . 48 figure 30. stop mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 31. sclk circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 33. stop mode recovery register 2 ((0f) dh:d2?d4, d6 write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
crimzon tm zlr16300 product specification ps021410-0605 list of figures vi figure 34. watch-dog timer mode register (write only) . . . . . . . . . . . . . . . . 55 figure 35. resets and wdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 36. tc8 control register ((0d) 00h: read/write except where noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 37. t8 and t16 common control functions ((0d) 01h: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 38. t16 control register ((0d) 02h: read/write except where noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 39. t8/t16 control register (0d) 03h: read/write (except where noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 40. voltage detection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 41. port configuration register (pcon) ((0f)00h: write only . . . . . . . 64 figure 42. stop mode recovery register ((0f) 0bh: d6?d0=write only, d7=read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 43. stop mode recovery register 2 ((0f) 0dh: d2?d4, d6 write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 44. watch-dog timer register ((0f) 0fh: write only) . . . . . . . . . . . . . 67 figure 45. port 2 mode register (f6h: write only). . . . . . . . . . . . . . . . . . . . . . 67 figure 46. port 3 mode register (f7h: write only) . . . . . . . . . . . . . . . . . . . . . 68 figure 47. port 0 register (f8h: write only) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 48. interrupt priority register (f9h: write only) . . . . . . . . . . . . . . . . . . 70 figure 49. interrupt request register (fah: read/write) . . . . . . . . . . . . . . . . 71 figure 50. interrupt mask register (fbh: read/write) . . . . . . . . . . . . . . . . . . . 71 figure 51. flag register (fch: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 52. register pointer (fdh: read/write) . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 53. stack pointer high (feh: read/write) . . . . . . . . . . . . . . . . . . . . . . 73 figure 54. stack pointer low (ffh: read/write) . . . . . . . . . . . . . . . . . . . . . . . 73 figure 55. 20-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 56. 20-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 57. 20-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 58. 28-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 59. 28-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 60. 28-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
crimzon tm zlr16300 product specification ps021410-0605 list of tables vii list of tables table 1. revision history of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 3. power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 4. 20-pin dip/soic/ssop pi n identification . . . . . . . . . . . . . . . . . . . . . 5 table 5. 28-pin dip/soic/ssop pi n identification . . . . . . . . . . . . . . . . . . . . . 6 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 8. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. port 3 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. ctr1(0d)01h t8 and t16 common functions . . . . . . . . . . . . . . . . 28 table 11. interrupt types, sources, and vectors . . . . . . . . . . . . . . . . . . . . . . 45 table 12. irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. smr2(f)0dh:stop mode recovery register 2* . . . . . . . . . . . . . . . 51 table 14. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 15. watch-dog timer time select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16. rom selectable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
crimzon tm zlr16300 product specification ps021410-0605 features 1 features table 1 lists the features of zilog ? ?s crimzon tm zlr16300 family members. ? low power consumption?5mw (typical) ? three standby modes: ? stop?1.3 a (typical) ? halt?0.5ma (typical) ? low voltage reset ? special architecture to automate both generation and reception of complex pulses or signals: ? one programmable 8-bit counter/timer with two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? six priority interrupts ? three external ? two assigned to counter/timers ? one low-voltage detection interrupt ? low voltage detection and high voltage detection flags ? programmable watch-dog timer (wdt) ? power-on reset (por) ? two independent comparators with programmable interrupt polarity ? selectable pull-up transistors on ports 0, 2, 3 table 1. features device rom (kb) ram* (bytes) i/o lines voltage range crimzon tm zlr16300 1, 2, 4, 8, 16 237 24, 16 2.0v?3.6v * general purpose
crimzon tm zlr16300 product specification ps021410-0605 general description 2 ? mask options ? port 0: 0?3 pull-ups ? port 0: 4?7 pull-ups ? port 2: 0?7 pull-ups ? port 3: 0?3 pull-ups ? watch-dog timer at power on reset general description the crimzon tm zlr16300 is a rom-based member of the mcu family of general purpose microcontrollers. with 1kb to 16kb of program memory and 237b of general purpose ram, zilog ? ?s cmos microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. the crimzon tm zlr16300 architecture (figures 1 and 2) is based on zilog ? ?s 8- bit microcontroller core with an expanded re gister file allowing access to regis- ter-mapped peripherals, input/output (i/o) circuits, and powerful counter/timer cir- cuitry. the z8 ? core offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many con- sumer, automotive, computer peripheral, and battery-operated hand-held applica- tions. there are three basic address spaces available to support a wide range of config- urations: program memory, register file and expanded register file. the regis- ter file is composed of 256b of ram. it includes three i/o port registers, 16 control and status registers, and 237 general-pur pose registers. the expanded register file consists of two additional register groups (f and d). to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the crimzon tm zlr16300 offers a new intelligent coun ter/timer architecture with 8-bit and 16-bit counter/timers (see figure 2). also included are a large number of user-selectable modes and two on-board co mparators to process analog signals with separate reference voltages. power connections use the conventional descriptions listed in table 2. table 2. power connections connection circuit device power v cc v dd ground gnd v ss
crimzon tm zlr16300 product specification ps021410-0605 general description 3 figure 1. functional block diagram z8? core port 2 port 0 p21 p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04 p05 p06 p07 p00 p01 p02 p03 i/o nibble programmable register file 256 x 8-bit register bus internal address bus internal data bus expanded register file expanded register bus z8 ? core counter/timer 8 8-bit counter/timer 16 16-bit v dd v ss xtal pref1/p30 p31 p32 p33 p34 p35 p36 p37 port 3 machine timing & instruction control power 4 4 rom up to 16k x 8 watch-dog timer low voltage detection high voltage detection power-on reset note: refer to the specific package for available pins.
crimzon tm zlr16300 product specification ps021410-0605 general description 4 figure 2. counter/timers diagram hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
crimzon tm zlr16300 product specification ps021410-0605 pin description 5 pin description the pin configuration for the 20-pin dip/ soic/ssop is illustrated in figure 3 and described in table 3. the pin configurat ion for the 28-pin dip/soic/ssop are depicted in figure 4 and described in table 4. figure 3. 20-pin dip/soic/ssop pin configuration table 3. 20-pin dip/soic /ssop pin id entification pin # symbol function direction 1?3 p25?p27 port 2, bits 5,6,7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8?10 p31?p33 port 3, bits 1,2,3 input 11,12 p34, p36 port 3, bits 4,6 output 13 p00/pref1/p30 port 0, bi t 0/analog reference input port 3, bit 0 input/output for p00 input for pref1/p30 14 p01 port 0, bit 1 input/output 15 v ss ground 16?20 p20?p24 port 2, bits 0,1,2,3,4 input/output p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 p24 p23 p22 p21 p20 v ss p01 p00/pref1/p30 p36 p34 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin dip soic ssop
crimzon tm zlr16300 product specification ps021410-0605 absolute maximum ratings 6 figure 4. 28-pin dip/soic/ssop pin configuration table 4. 28-pin dip/soic /ssop pin id entification absolute maximum ratings stresses greater than those listed in table 5 might cause permanent damage to the device. this rating is a stress rating only. functional operation of the device at pin symbol direction description 1-3 p25-p27 input/output port 2, bits 5,6,7 4-7 p04-p07 input/output port 0, bits 4,5,6,7 8v dd power supply 9 xtal2 output crystal, oscillator clock 10 xtal1 input crystal, oscillator clock 11?13 p31-p33 input port 3, bits 1,2,3 14 p34 output port 3, bit 4 15 p35 output port 3, bit 5 16 p37 output port 3, bit 7 17 p36 output port 3, bit 6 18 pref1 input analog ref input; connect to v cc if not used port 3 bit 0 19-21 p00-p02 input/output port 0, bits 0,1,2 22 v ss ground 23 p03 input/output port 0, bit 3 24-28 p20-p24 input/output port 2, bits 0-4 p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 pref1/p30 p36 p37 p35 p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 1 28-pin pdip soic ssop 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
crimzon tm zlr16300 product specification ps021410-0605 standard test conditions 7 any condition above those indicated in the operational sections of these specifica- tions is not implied. exposure to abso lute maximum rating conditions for an extended period might af fect device reliability. standard test conditions the characteristics listed in this product specification apply for standard test con- ditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (see figure 5). figure 5. test load diagram table 5. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias 0 +70 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +4.0 v 1 voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 ma maximum output current from active output pin -25 +25 ma maximum current into v dd or out of v ss 75 ma note: 1. this voltage applies to all pins except the following: v dd . from output under test 150 pf
crimzon tm zlr16300 product specification ps021410-0605 dc characteristics 8 capacitance table 6 lists the capacitances. dc characteristics table 6. capacitance parameter maximum input capacitance 12pf output capacitance 12pf i/o capacitance 12pf note: t a = 25c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd table 7. dc characteristics t a = 0c to +70c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 v 3.6 v see note 5 v ch clock input high voltage 2.0-3.6v 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-3.6v v ss ?0.3 0.5 v driven by external clock generator v ih input high voltage 2.0-3.6v 0.7 v cc v cc +0.3 v v il input low voltage 2.0-3.6v v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-3.6v v cc ?0.4 v i oh = ?0.5ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-3.6v v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-3.6v 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-3.6v 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-3.6v 25 mv v ref comparator reference voltage 2.0-3.6v 0 v dd -1.75 v i il input leakage 2.0-3.6v ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 225 675 k ? v in = 0v; pullups selectedby mask option 3.6v 75 275 k ? i ol output leakage 2.0-3.6v ?1 1 av in = 0v, v cc i cc supply current 2.0 v 3.6 v 1.2 2.1 3 5 ma ma at 8.0mhz at 8.0mhz 1, 2 1, 2
crimzon tm zlr16300 product specification ps021410-0605 dc characteristics 9 i cc1 standby current (halt mode) 2.0 v 3.6 v 0.5 0.8 1.6 2.0 ma ma v in = 0v, clock at 8.0mhz same as above 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0 v 3.6 v 2.0 v 3.6 v 1.2 1.4 3.5 6.5 8 10 20 30 a a a a v in = 0 v, v cc wdt is not running same as above v in = 0 v, v cc wdt is running same as above 3 3 3 3 i lv standby current (low voltage) 0.8 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.8 2.0 v 8mhz maximum ext. clk freq. v lvd vcc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 f), physically close to vdd and v ss pins if operating voltage fluctuations are anticiipated, such as those resulting from driving an ir led. 6. comparators and timers are on. interrupt disabled. 7. typical vales shown are at 25 degrees c. table 7. dc characteristics (continued) t a = 0c to +70c units conditions notes symbol parameter v cc min typ(7) max
crimzon tm zlr16300 product specification ps021410-0605 ac characteristics 10 ac characteristics figure 6 and table 8 describe the alternating current (ac) characteristics. figure 6. ac timing diagram clock stop mode recovery source clock setup 1 22 3 3 t in 7 4 5 6 7 irq n 8 9 11 10
crimzon tm zlr16300 product specification ps021410-0605 ac characteristics 11 table 8. ac characteristics t a =0c to +70c 8.0mhz watch-dog timer mode register (d1, d0) no symbol parameter v cc minimum maximum units notes 1 tpc input clock period 2.0?3.6 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0?3.6 25 ns 1 3 twc input clock width 2.0?3.6 37 ns 1 4 twtinl timer input low width 2.0 3.6 100 70 ns 1 5 twtinh timer input high width 2.0?3.6 3tpc 1 6 tptin timer input period 2.0?3.6 8tpc 1 7 trtin,tftin timer input rise and fall timers 2.0?3.6 100 ns 1 8 twil interrupt request low time 2.0 3.6 100 70 ns 1, 2 9 twih interrupt request input high time 2.0?3.6 10tpc 1, 2 10 twsm stop-mode recovery width spec 2.0?3.6 12 10tpc ns 3 4 11 tost oscillator start-up time 2.0?3.6 5tpc 4 12 twdt watch-dog timer delay time 2.0?3.6 2.0?3.6 2.0?3.6 2.0?3.6 10 20 40 160 ms ms ms ms 0, 0 0, 1 1, 0 1, 1 13 t por power-on reset 2.0?3.6 2.5 10 ms notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33?p31). 3. smr ? d5 = 1. 4. smr ? d5 = 0.
crimzon tm zlr16300 product specification ps021410-0605 pin functions 12 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. additionally, an external single-phase clock can be connected to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. port 0 (p07?p00) port 0 is an 8-bit, bidirectional, cmos-c ompatible port. these eight i/o lines are configured under software control as a nibble i/o port. the output drivers are push-pull or open-drain controlled by bit d2 in the pcon register. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. af ter a hardware reset, port 0 is configured (figure 7) as an input port. an optional pull-up transistor is available as a mask option on all port 0 bits with nibble select. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. the port 0 direction is reset to be input following an smr. notes:
crimzon tm zlr16300 product specification ps021410-0605 pin functions 13 figure 7. port 0 configuration port 2 (p27?p20) port 2 is an 8-bit, bidirectional, cmos-c ompatible i/o port (see figure 8). these eight i/o lines can be independently config ured under software control as inputs or outputs. port 2 is always available fo r i/o operation. a mask option is available to connect eight pull-up transistors on this port. bits programmed as outputs are globally programmed as either push-pull or open-drain. the por resets with the eight bits of port 2 configured as inputs. port 2 also has an 8-bit input or and and gate, which can be used to wake up the part. p20 can be programmed to ac cess the edge-detection circuitry in demodulation mode. 4 4 zlr16300 port 0 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc mask option
crimzon tm zlr16300 product specification ps021410-0605 pin functions 14 figure 8. port 2 configuration port 3 (p37?p30) port 3 is an 8-bit, cmos-compatible fixed i/o port (see figure 9). port 3 consists of four fixed input (p33?p30) and four fixed output (p37?p34), which can be con- figured under software control for interrupt and as output from the counter/timers. p30, p31, p32, and p33 are standard cmos inputs; p34, p35, p36, and p37 are push-pull outputs. port 2 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc mask option zlr16300 rom
crimzon tm zlr16300 product specification ps021410-0605 pin functions 15 figure 9. port 3 configuration two on-board comparators process analog signals on p31 and p32, with refer- ence to the voltage on pref1 and p33. the analog function is enabled by program- ming the port 3 mode register (bit 1). p31 and p32 are programmable as rising, falling, or both edge triggered interrupts (irq register bits 6 and 7). pref1 and p33 are the comparator reference voltage inputs. access to the counter timer edge- detection circuit is through p31 or p 20 (see ?t8 and t16 common functions??t8 - port 3 (i/o) p32 (an2) p31 (an1) pref1 from stop mode recovery source of smr irq2, p31 data latch pref1/p30 p31 p32 p33 p34 p35 p36 p37 d1 1 = analog 0 = digital r247 = p3m + - + irq0, p32 data latch irq1, p33 data latch comp 1 comp2 dig. an. zlr16300 rom p33 (ref2)
crimzon tm zlr16300 product specification ps021410-0605 pin functions 16 and t16 common functions?ctr1(0d)01h? on page 28). other edge detect and irq modes are described in table 9. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery (smr) source, these inputs must be placed into digital mode. 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 10). control is performed by pr ogramming bits d5?d4 of ctr1, bit 0 of ctr0, and bit 0 of ctr2. table 9. port 3 pin function summary pin i/o counter/timers comparator interrupt pref1/p30 in rf1 p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p35 out t16 p36 out t8/16 p37 out ao2 p20 i/o in note:
crimzon tm zlr16300 product specification ps021410-0605 pin functions 17 figure 10. port 3 counter/timer output configuration pad p34 comp1 v dd mux pcon, d0 mu x ctr0, d0 p31 p30 (pref1) p34 data t8_out + pad p35 v dd mux ctr2, d0 out 35 t16_out pad p36 v dd mux ctr1, d6 out 36 t8/t16_out pad p37 v dd mux pcon, d0 p37 data - p31 p3m d1 comp2 p32 p33 + - p32 p3m d1
crimzon tm zlr16300 product specification ps021410-0605 functional description 18 comparator inputs in analog mode, p31 and p32 have a comparator front end. the comparator reference is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 are diverted to the smr sources (excluding p31, p32, and p33) as indicated in figure 9 on page 15. in digital mode, p33 is used as d3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery source, these inputs must be placed into digital mode. comparator outputs these channels can be programmed to be output on p34 and p37 through the pcon register. functional description these devices incorporate special functions to enhance the z8 ? ?s functionality in consumer and battery-operated applications. program memory these devices address from 1kb to16kb of program memory. the first 12 bytes are reserved for interrupt vectors. these locations contain the six 16-bit vectors that correspond to the six available interrupts. see figure 11. ram the zlr16300 product family features 237 bytes of ram. note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 19 figure 11. program memory map on-chip rom reset start address irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 12 11 10 9 8 7 6 5 4 3 2 1 0 maximum rom size location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) not accessible
crimzon tm zlr16300 product specification ps021410-0605 functional description 20 expanded register file the register file has been expanded to al low for additional system control regis- ters and for mapping of additional peripher al devices into the register address area. the z8 ? register address space (0 th rough15 (ofh) has been implemented as 16 banks, with 16 registers per bank . these register banks are known as the erf (expanded register file). bits 7?4 of register rp select the working register group. bits 3?0 of register rp select the expanded register file bank. an expanded register bank is also referred to as an expanded register group (see figure 12). note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 21 figure 12. expanded register file architecture uuuuuuu0 00000000 00000000 00000000 00 0f 7f f0 ff ff spl 00000000 uuuuuuuu 00000000 uuuuuuuu uuuuuuuu uuuuuuuu 11111111 00000000 11001111 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu fe sph fd rp fc flags fb imr fa irq f9 ipr f8 p01m f7 p3m f6 p2m f5 reserved f4 reserved f3 reserved f2 reserved f1 reserved f0 reserved d7 d6 d5 d4 d3 d2 d1 d0 uu001101 u01000u0 11111110 (f) 0f wdtmr (f) 0e reserved (f) 0d smr2 (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon 76543210 expanded register bank pointer working register uuuuuuuu uuuuuuuu 00000000 (d) 0c lvd (d) 0b hi8 (d) 0a lo8 (d) 09 hi16 (d) 08 lo16 (d) 07 tc16h (d) 06 tc16l (d) 05 tc8h (d) 04 tc8l (d) 03 ctr3 (d) 02 ctr2 (d) 01 ctr1 (d) 00 ctr0 group pointer register file (bank 0)** 00011111 * * 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 u = unknown * is not reset with a stop-mode recovery ** all addresses are in hexadecimal is not reset with a stop-mode recovery, except bit 0 bit 5 is not reset with a stop-mode recovery bits 5,4,3,2 not reset with a stop-mode recovery bits 5 and 4 not reset with a stop-mode recovery bits 5,4,3,2,1 not reset with a stop-mode recovery expanded reg. bank 0/group (0) (0) 03 p3 (0) 02 p2 0 u u * * * * * * * * * * * expanded reg. bank f/group 0** register** register pointer z8 ? standard control registers expanded reg. bank d/group 0 reset condition u (0) 00 p0 reserved note: a write has no effect. will always read back ff. note
crimzon tm zlr16300 product specification ps021410-0605 functional description 22 the upper nibble of the register pointer (see figure 13) selects which working reg- ister group, of 16 bytes in the register file, is accessed out of the possible 256. the lower nibble selects the expanded register file bank and in the case of the crim- zon tm zlr16300 family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed. any other value from 1h to fh exchanges the lower 16 registers to the selected expanded register bank. figure 13. register pointer example: (see figure 12 on page 21) r253 rp = 00h r0 = port 0 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = ctr3 r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000
crimzon tm zlr16300 product specification ps021410-0605 functional description 23 the counter/timers are mapped into erf group d. access is easily performed using the following: ld rp, #0dh ;select erf d for access to bank d ;(working register group 0) ld r0,#xx ;load ctr0 ld 1, #xx ;load ctr1 ld r1, 2 ;ctr2 ctr1 ld rp, #0dh ;select erf d for access to bank d ; (working register group 0) ld rp, #7dh ;select expanded register bank d and working ;register group 7 of bank 0 for access. ld 71h, 2 ;ctrl2 register 71h ld r1, 2 ;ctrl2 register 71h register file the register file (bank 0) consists of 3 i/o port registers, 237 general-purpose reg- isters, 16 control and status registers (r0, r2, r3, r4?r239, and r240?r255, respectively), and two expanded register banks d (see table 10) and f. instruc- tions can access registers directly or i ndirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the register pointer (figure 14). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group. register address e0h?efh can only be accessed through working registers and indirect addressing modes. note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 24 figure 14. register pointer?detail stack the internal register file is used for the stack. an 8-bit stack pointer spl (r255) is used for the internal stack that resides in the general-purpose registers (r4? r239). sph (r254) can be used as a general-purpose register. r 7 r 6 r 5 r 4 r 3 r 2 r 1 r the upper nibble of the register file address provided by the register pointer specifies the active working-register group. specified working register group register group 1 register group 0 i/o ports r253 the lower nibble of the register file address provided by the instruction points to the specified register. * rp = 00: selects register bank 0, working register group 0 r15 to r0 r15 to r4 * r3 to r0 * 40 3f 30 2f 20 1f 10 0f 00 register group 2 4f ff f0
crimzon tm zlr16300 product specification ps021410-0605 functional description 25 timers t8_capture_hi?hi8(0d)0bh this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 1. t8_capture_lo?l08(0d)0ah this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 0. t16_capture_hi?hi16(0d)09h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ms-byte of the data. t16_capture_lo?l016(0d)08h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ls-byte of the data. counter/timer2 ms-byte hold register?tc16h(0d)07h field bit position description t8_capture_hi [7:0] r/w captured data - no effect field bit position description t8_capture_l0 [7:0] r/w captured data - no effect field bit position description t16_capture_hi [7:0] r/w captured data - no effect field bit position description t16_capture_lo [7:0] r/w captured data - no effect field bit position description t16_data_hi [7:0] r/w data
crimzon tm zlr16300 product specification ps021410-0605 functional description 26 counter/timer2 ls-byte hold register?tc16l(0d)06h counter/timer8 high hold register?tc8h0(d)05h counter/timer8 low hold register?tc8l(0d)04h ctr0 counter/timer8 control register?ctr0(0d)00h table 10 lists and briefly describes the fields for this register. field bit position description t16_data_lo [7:0] r/w data field bit position description t8_level_hi [7:0] r/w data field bit position description t8_level_lo [7:0] r/w data table 10. ctr0(0d)00h counter/timer8 control register field bit position value description t8_enable 7------- r/w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0* 1 modulo-n single pass time_out --5------ r/w 0** 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0** 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data ca pture interrupt enable data capture interrupt
crimzon tm zlr16300 product specification ps021410-0605 functional description 27 t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter rel oads the initial value when the terminal count is reached. when set to 1 (single-pass), the counter stops when the termi- nal count is reached. timeout this bit is set when t8 times out (terminal co unt reached). to reset this bit, write a 1 to its location. writing a 1 is the only way to reset the terminal count status condition. reset this bit before using/enabling the counter/timers. the first clock of t8 might not have complete clock width and can occur any time when enabled. take care when using the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-m odify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and then written back into the registers. t8 clock these bits define the frequency of the input signal to t8. counter_int_mask ------1- r/w 0** 1 disable time-o ut interrupt enable time-out interrupt p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: * indicates the value at power-on reset. * * indicates the value upon power-on reset. not reset with a stop mode recovery. table 10. ctr0(0d)00h counter/timer8 control register (continued) field bit position value description caution: note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 28 capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in capture mode. counter_int_mask set this bit to allow an interrupt when t8 has a timeout. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. t8 and t16 common functions?ctr1(0d)01h this register controls the functions in common with the t8 and t16. table 11 lists and briefly describes the fields for this register. table 11. ctr1(0d)01h t8 and t16 common functions field bit position value description mode 7------- r/w 0* 1 transmit mode demodulation mode p36_out/ capture_input -6------ r/w 0* 1 0* 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00** 01 10 11 00** 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved
crimzon tm zlr16300 product specification ps021410-0605 functional description 29 mode if the result is 0, the counter/timers are in transmit mode; otherwise, they are in demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whethe r p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/ timers is from p20 or p31. transmit_submode/ glitch_filter ----32-- r/w 00 01 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle reserved initial_t8_out/ rising edge ------1- r/w r w 0 1 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling_edge -------0 r/w r w 0 1 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 note: *default at power-on reset. * * indicates the value upon power-on reset. not reset with a stop mode recovery. table 11. ctr1(0d)01h t8 and t16 common functions (continued) field bit position value description
crimzon tm zlr16300 product specification ps021410-0605 functional description 30 if the input signal is from port 31, a capture event may also generate an irq2 interrupt. to prevent generating an irq2, either disable the irq2 interrupt by clearing its imr bit d2 or use p20 as the input. t8/t16_logic/edge_detect in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defin es which edge should be detected by the edge detector. transmit_submode/glitch filter in transmit mode, this field defines whether t8 and t16 are in the ping-pong mode or in independent normal operation mode. setting this field to ?normal operation mode? terminates the ?ping- pong mode? operation. when set to 10, t16 is immediately forced to a 0; a setting of 11 forces t16 to output a 1. in demodulation mode, this field defines the width of the glitch that must be fil- tered out. initial_t8_out/rising_edge in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the output of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset the mode, a 1 should be written to this location. initial_t16 out/falling _edge in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3; d2). when the counter is not enabled and this bit is set, t16_out is set to the opposit e state of this bit. this ensures that when the clock is enabled, a transition occu rs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 should be written to this location. modifying ctr1 (d1 or d0) while the counters are enabled causes unpredictable output from t8/16_out. ctr2 counter/timer 16 control register?ctr2(0d)02h table 12 lists and briefly describes the fields for this register. note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 31 t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. when set to 1, the counter stops when the terminal count is reached. table 12. ctr2(0d)02h: counter/timer16 control register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0** 1 0 1 no counter timeout counter timeout occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00** 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0* disable timeout int. enable timeout int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 note: *indicates the value upon power-on reset. ** indicates the value upon power-on reset. not reset with a stop mode recovery.
crimzon tm zlr16300 product specification ps021410-0605 functional description 32 in demodulation mode, when set to 0, t16 captures and reloads on detection of all the edges. when set to 1, t16 capt ures and detects on the first edge but ignores the subsequent edges. for details , see the description of t16 demodula- tion mode on page 40. time_out this bit is set when t16 times out (terminal count reached). to reset the bit, write a 1 to this location. t16_clock this bit defines the frequency of the input signal to counter/timer16. capture_int_mask this bit is set to allow an interrupt when data is captured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. p35_out this bit defines whether p35 is used as a normal output pin or t16 output. ctr3 t8/t16 control register?ctr3(0d)03h table 13 lists and briefly describes the fields for this register. this register allow the t8 and t16 counters to be synchronized. table 13. ctr3(0d)03h t8/t16 control register t16_enable 7------- r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter t8 enable -6------ r/w 0** 1 0 1 counter disabled counter enabled stop counter enable counter sync mode --5----- r/w 0* 1 disable sync mode enable sync mode reserved ---43210 r/w 1 x always reads 11111 no effect * indicates the value upon power-on reset. * ** indicates the value upon power-on reset. not reset with a stop mode recovery.
crimzon tm zlr16300 product specification ps021410-0605 functional description 33 counter/timer functional blocks input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5? d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal t hat have a width less than specified (ctr1 d3, d2) are filtered out (see figure 15). figure 15. glitch filter circuitry t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 16. mux glitch filter edge detector p31 p20 pos edge neg edge ctr1 d5,d4 ctr1 d6 ctr1 d3, d2
crimzon tm zlr16300 product specification ps021410-0605 functional description 34 figure 16. transmit mode flowchart set timeout status bit (ctr0 d5) and generate timeout_int if enabled set timeout status bit (ctr0 d5) and generate timeout_int if enabled t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes ctr1, d1 value reset t8_enable bit 0 1 load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single modulo-n t8_out value 0 enable t8 no t8_timeout ye s pass? load tc8h set t8_out load tc8l reset t8_out 1
crimzon tm zlr16300 product specification ps021410-0605 functional description 35 when t8 is enabled, the output t8_out switches to the initial value (ctr1, d1). if the initial value (ctr1, d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter. in single-pass mode (ctr0, d6), t8 counts down to 0 and stops, t8_out toggles, the timeout status bit (ctr0, d5) is set, and a timeout interrupt can be generated if it is enabled (ctr0, d1). in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. from that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, and sets the timeout sta- tus bit (ctr0, d5), thereby generating an interrupt if enabled (ctr0, d1). one cycle is complete. t8 t hen loads from tc8h or tc8l according to the t8_out level and repeats the cycle. see figure 17. figure 17. 8-bit counter/timer circuits the values in tc8h or tc8l can be modi fied at any time. the new values take effect when they are loaded. to ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer. an initial count of 1 is not allowed (a non-function occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh . ctr0 d1 negative edge positive edge z8 ? data bus irq4 ctr0 d2 sclk z8 ? data bus ctr0 d4, d3 clock t8_out lo8 tc8h tc8l clock select 8-bit counter t8 hi8 caution:
crimzon tm zlr16300 product specification ps021410-0605 functional description 36 the letter h denotes hexadecimal values. transition from 0 to ffh is not a timeout condition. using the same instructions for stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counter/timers must be stopped. second, the status bits must be reset. these commands are required because it takes one counter/timer clock interv al for the initiated event to actually occur. see figure 18 and figure 19. figure 18. t8_out in single-pass mode figure 19. t8_out in modulo-n mode t8 demodulation mode the user must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1, d5; d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current value of t8 is comple- mented and put into one of the capture registers. if it is a positive edge, data is put into lo8; if it is a negative edge, data is put into hi8. from that point, one of the n ote: caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 d1) t8_out toggles; timeout interrupt counter enable command; t8_out switches to its initial value (ctr1 d1) timeout interrupt timeout interrupt t8_out t8_out toggles tc8l tc8h tc8h tc8l tc8l ...
crimzon tm zlr16300 product specification ps021410-0605 functional description 37 edge detect status bits (ctr1, d1; d0) is set, and an interrupt can be generated if enabled (ctr0, d2). meanwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the timeout status bit (ctr0, d5) is set, and an interrupt can be generated if enabled (ctr0, d1). t8 then continues counting from ffh (see figure 21 and figure 21). figure 20. demodulation mode count capture flowchart t8 (8-bit) count capture t8 enable (set by user) no yes edge present what kind of edge t8 hi8 no yes negative ffh t8 positive t8 lo8
crimzon tm zlr16300 product specification ps021410-0605 functional description 38 figure 21. demodulation mode flowchart t8 (8-bit) capture mode t8 enable ctr0, d7 no yes ffh tc8 first edge present enable tc8 t8_enable bit set edge present t8 timeout set edge present status bit and trigger data capture int. if enabled set timeout status bit and trigger timeout int. if enabled continue counting disable tc8 no yes no yes yes yes no no
crimzon tm zlr16300 product specification ps021410-0605 functional description 39 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is dependent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enabled or not by programming ctr1 d3; d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, d0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt (ctr2, d1) is generated (if enabled), and a status bit (ctr2, d5) is set. see figure 22. figure 22. 16-bit counter/timer circuits global interrupts override this function as described in ?interrupts? on page 43. if t16 is in single-pass mode, it is stopped at this point (see figure 23). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting contin- ues (see figure 24). the values in tc16h and tc16l can be modified at any time. the new values take effect when they are loaded. ctr2 d1 negative edge positive edge z8 ? data bus irq3 ctr2 d2 sclk z8 ? data bus ctr2 d4, d3 clock t16_out lo16 tc16h tc16l clock select 16-bit counter t16 hi16 note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 40 do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh . transition from 0 to ffffh is not a timeout condition. figure 23. t16_out in single-pass mode figure 24. t16_out in modulo-n mode t16 demodulation mode the user must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 d5; d4) is detected, t16 captures hi16 and lo16, re loads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt is generated if enabled (ctr2, d2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to meas ure space time, the length of time between bursts of carrier signal (marks). caution: tc16h*256+tc16l counts ?counter enable? command t16_out switches to its initial value (ctr1 d0) t16_out toggles, timeout interrupt tc16h*256+tc16l tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, timeout interrupt t16_out toggles, timeout interrupt ?counter enable? command, t16_out switches to its initial value (ctr1 d0) tc16_out ...
crimzon tm zlr16300 product specification ps021410-0605 functional description 41 if d6 of ctr2 is 1 t16 ignores the subsequent edges in th e input signal and continues counting down. a timeout of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if the d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it), t16 cap- tures and reloads on the next edge (rising, falling, or both depending on ctr1, d5; d4), continuing to ignore subsequent edges. this t16 mode generally measures mark time , the length of an active carrier sig- nal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 d5) is set, and an interrupt timeout can be generated if enabled (ctr2 d1). ping-pong mode this operation mode is only valid in tr ansmit mode. t8 and t16 must be pro- grammed in single-pass mode (ctr0, d6; ctr2, d6), and ping-pong mode must be programmed in ctr1, d3; d2. the user can begin the operation by enabling either t8 or t16 (ctr0, d7 or ct r2, d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1, d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is dis- abled, and t16 is enabled. t16_out then swit ches to its initial value (ctr1, d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enabl ed again, repeating the entire cycle. inter- rupts can be allowed when t8 or t16 reaches terminal control (ctr0, d1; ctr2, d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 25. enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. disable the counter/timers and reset the status flags before instituting this operation. note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 42 figure 25. ping-pong mode diagram initiating ping-pong mode first, make sure both counter/timers are not running. set t8 into single-pass mode (ctr0, d6), set t16 into single -pass mode (ctr2, d6), and set the ping- pong mode (ctr1, d2; d3). these instructions can be in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). see figure 25. figure 26. output circuit the initial value of t8 or t16 must not be 1 . if you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. enable tc8 enable timeout tc16 ping-pong ctr1 d3,d2 timeout t16_out mux ctr1 d3 t8_out p34 and/or/nor/nand logic mux mux mux p35 p36 p34_internal ctr1 d5, d4 p36_internal p35_internal ctr1, d2 ctr0 d0 ctr1 d6 ctr2 d0
crimzon tm zlr16300 product specification ps021410-0605 functional description 43 during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alter- nately by hardware. the timeout bits (ctr 0, d5; ctr2, d5) are set every time the counter/timers reach the terminal count. timer output the output logic for the timers is illustrated in figure 26. p34 is used to output t8- out when d0 of ctr0 is set. p35 is used to output the value of t16-out when d0 of crtr2 is set. when d6 of ctr1 is et, p36 outputs the logic combination of t8-out and t16-out determined by d5 and d4 of ctr1. interrupts the crimzon tm zlr16300 features six different interrupts (table 14). the inter- rupts are maskable and prioritized (figure 27). the six sources are divided as fol- lows: three sources are claimed by port 3 lines p33?p31, two by the counter/ timers (table 14) and one for low voltage detection. the interrupt mask register (globally or individually ) enables or disables the six interrupt requests. the source for irq is determined by bit 1 of the port 3 mode register (p3m). when in digital mode, pin p33 is the source. when in analog mode the output of the stop mode recovery source logic is used as the source for the interrupt. see figure 32, stop mode recovery source, on page 52.
crimzon tm zlr16300 product specification ps021410-0605 functional description 44 figure 27. interrupt block diagram low-voltage detection timer 8 timer 16 interrupt edge select imr ipr priority logic irq 6 irq2 irq0 irq1 irq3 irq4 irq5 p31 p32 irq register d6, d7 global interrupt enable interrupt request vector select d1 of p3m register p33 0 1 stop mode recovery source
crimzon tm zlr16300 product specification ps021410-0605 functional description 45 when more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the inte rrupt priority register. an interrupt machine cycle activates when an interrupt request is granted. as a result, all sub- sequent interrupts are disabled, and the program counter and status flags are saved. the cycle then branches to the program memory vector location reserved for that interrupt. all crimzon tm zlr16300 interrupts are vectored through loca- tions in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to determine which of the interrupt requests require service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered. these interrupts are programmabl e by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6. the configuration is indicated in table 15. table 14. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), ris ing, falling edge triggered irq1 p33 2,3 external (p33), falling edge triggered irq2 p31, t in 4,5 external (p31), rising, falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal irq5 lvd 10,11 internal table 15. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r/f r/f note: f = falling edge; r = rising edge
crimzon tm zlr16300 product specification ps021410-0605 functional description 46 clock the device?s on-chip oscillator has a hi gh-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ? . the on-chip oscillator can be driven with a suitable external clock source. the crystal must be connected across xtal1 and xtal2 using the recommended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. figure 28. oscillator configuration power-on reset a timer circuit clocked by a dedicated on-board rc-oscillator is used for the power-on reset (por) timer func tion. the por time allows v dd and the oscilla- tor circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: ? power fail to power ok status, including waking up from v bo standby ? stop-mode recovery (if d5 of smr = 1) ? wdt timeout c1 c2 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 crystal c1, c2 = 33 pf typ* f = 8mhz * preliminary value including pin parasitics external clock ceramic resonator f = 8mhz
crimzon tm zlr16300 product specification ps021410-0605 functional description 47 the por timer is 2.5 ms minimum. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock). halt mode this instruction turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external interrupts ir q0, irq1, irq2, irq3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or inter- nally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruc- tion after the halt. stop mode this instruction turns off the internal cloc k and external crystal oscillation, reduc- ing the standby current to 10 a or less. stop mode is terminated only by a reset, such as wdt timeout, por or smr. thi s condition causes the processor to restart the application program at address 000ch . in order to enter stop (or halt) mode, first flush the instru ction pipeline to avoid sus pending execution in mid- instruction. execute an nop instruction (opcode = ffh ) immediately before the appropriate sleep instruction, as follows:
crimzon tm zlr16300 product specification ps021410-0605 functional description 48 ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration register the port configuration (pcon) register (figure 29) configures the comparator output on port 3. it is located in the expanded register file at bank f, location 00. pcon (0f) 00h figure 29. port configuration register (pcon) (write only) comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the compar- ator outputs to p34 and p37, and a 0 releases the port to its standard i/o configu- ration. port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output reserved (must be 1) port 0 0: open-drain 1: push-pull* reserved (must be 1) * default setting after reset
crimzon tm zlr16300 product specification ps021410-0605 functional description 49 stop-mode recovery register (smr) this register selects the clock divide value and determines the mode of stop mode recovery (figure 30). all bits are write only except bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level at the xor- gate input (figure 32 on page 52) is requir ed from the recovery source. bit 5 con- trols the reset delay after recovery. bits d2, d3, and d4 of the smr register spec- ify the source of the stop-mode recovery signal. bits d0 determines if sclk/ tclk are divided by 16 or not. the smr is located in bank f of the expanded register file at address 0bh .
crimzon tm zlr16300 product specification ps021410-0605 functional description 50 smr (0f) 0bh figure 30. stop mode recovery register sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk (figure 31). this control selectively reduces device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop-mode recovery, this bit is set to 0. d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * * 1 on reserved (must be 0) stop-mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * 1 stop recovery * * * default after power on reset or watch-dog reset * * default setting after reset and stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source.
crimzon tm zlr16300 product specification ps021410-0605 functional description 51 figure 31. sclk circuit stop-mode recovery register 2?smr2(0f)0dh table 16 lists and describes t he fields for this register. stop-mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery (figure 32 and table 17). table 16. smr2(f)0dh:stop mode recovery register 2* field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0 ? 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000 ? 001 010 011 100 101 110 111 a. por only b. nand of p23?p20 c. nand of p27?p20 d. nor of p33?p31 e. nand of p33?p31 f. nor of p33?p31, p00, p07 g. nand of p33?p31, p00, p07 h. nand of p33?p31, p22?p20 reserved ------10 00 reserved (must be 0) notes: * port pins configured as outputs are ignored as an smr recovery source. ? indicates the value at power-on reset sclk tclk smr, d0 2 osc 16
crimzon tm zlr16300 product specification ps021410-0605 functional description 52 figure 32. stop mode recovery source smr2 d4 d3 d2 100 smr2 d4 d3 d2 111 smr d4d3d2 010 smr d4d3d2 111 smr d4d3d2 101 smr d4d3d2 100 smr d4d3d2 011 smr d4d3d2 000 smr d4d3d2 110 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr2 d4 d3 d2 001 smr2 d4 d3 d2 000 smr2 d4 d3 d2 010 smr2 d4 d3 d2 011 smr2 d4 d3 d2 101 smr2 d4 d3 d2 110 vcc p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p07 p31 p32 p33 p00 p07 p31 p32 p33 p20 p21 smr d6 smr2 d6 to reset and wdt circuitry (active low)
crimzon tm zlr16300 product specification ps021410-0605 functional description 53 any port 2 bit defined as an output drives the corresponding input to the default state. this condition allows the remaining inputs to control the and/or function. refer to smr2 register on page 54 for other recover sources. stop mode recovery delay select (d5) this bit, if low, disables the t por delay after stop mode recovery. the default configuration of this bit is 1. if the ?fast? wake up is selected, the stop mode recovery source must be kept active for at least 10 tpc. this bit must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stabilize before executing instructions. stop mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the crimzon tm zlr16300 from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when the device is recovered from stop mode. the bit is set to 0 when the device rese t is other than stop mode recovery (smr). table 17. stop mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 001reserved 010p31 transition 011p32 transition 100p33 transition 101p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note: note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 54 stop mode recovery register 2 (smr2) this register determines the mode of stop mode recovery for smr2 (figure 33). smr2 (0f) dh figure 33. stop mode recovery register 2 ((0f) dh:d2?d4, d6 write only) if smr2 is used in conjunction with smr, either of the specified events causes a stop mode recovery. port pins configured as outputs are ignored as an smr or smr2 recovery source. for example, if the nand or p23?p20 is selected as the recovery source and p20 is configured as an output, the remaining smr pins (p23?p21) form the nand equation. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low * 1 high reserved (must be 0) note: if used in conjunction with sm r, either of the two specified ev ents causes a stop-mode recovery. * default setting after reset * * at the xor gate input note:
crimzon tm zlr16300 product specification ps021410-0605 functional description 55 watch-dog timer mode register (wdtmr) the watch-dog timer (wdt) is a retriggerable one-shot timer that resets the z8 ? if it reaches its terminal count. the wdt must initially be enabled by executing the wdt instruction. on subsequent executions of the wdt instruction, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source the internal rc-oscillator. bits 0 and 1 of the wdt register control a tap circuit that determines th e minimum timeout period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop. bits 4 through 7 are reserved (figure 34). this register is accessible only during the first 60 processor cycles (120 xtal clocks) from the execution of the first instruction after power-on-reset, watch-dog reset, or a stop-mode recovery (figure 33). after this point, the register cannot be modified by any means (intentional or otherwise). the wdtmr cannot be read. the register is located in bank f of the expanded register file at address location 0fh . it is organized as illustrated in figure 34. wdtmr (0f) 0fh figure 34. watch-dog timer mode register (write only) wdt time select (d0, d1) this bit selects the wdt time period. it is configured as indicated in table 18. d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset
crimzon tm zlr16300 product specification ps021410-0605 functional description 56 wdtmr during halt (d2) this bit determines whether or not the wdt is active during halt mode. a 1 indi- cates active during halt. the default is 1. see figure 35. figure 35. resets and wdt table 18. watch-dog timer time select d1 d0 timeout of internal rc-oscillator 0010 ms min. 0120 ms min. 1040 ms min. 1 1 160 ms min. - * clr1 and clr2 enable the wdt/por and 18 clock reset timers respectively upon a low-to-high input translation. + from stop mode recovery source stop delay select (smr) 5 clock filter *clr2 18 clock reset clk generator reset wdt tap select por 10 ms 20 ms 40 ms 160 ms clk *clr1 wdt/por counter chain internal rc oscillator. wdt v dd low operating voltage det. vbo v dd internal reset active high 12-ns glitch filter xtal
crimzon tm zlr16300 product specification ps021410-0605 functional description 57 wdtmr during stop (d3) this bit determines whether or not the wd t is active during stop mode. a 1 indi- cates active during stop. the default is 1. rom selectable options there are five rom selectable options to choose from based on rom code requirements. these options are listed in table 19. voltage brown-out/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is pre- served. when the power level is returned to above v bo , the device performs a por and functions normally. low-voltage detection register?lvd(0d)0ch voltage detection does not work at stop mode. it must be disabled during stop mode in order to reduce current. table 19. rom selectable options port 00?03 pull-ups on/off port 04?07 pull-ups on/off port 20?27 pull-up port 3 pull-ups on/off port 3 pull-ups on/off watch-dog timer at power-on reset on/off field bit position description lvd 765432--- reserved -----2 r 1 0* hvd flag set hvd flag reset ------1- r 1 0* lvd flag set lvd flag reset -------0 r/w 1 0* enable vd disable vd * default after por note:
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0d) 58 do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. voltage detection and flags the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detection is enabled when bit 0 of lvd register is set. when voltage detection is enabled, the the v cc level is monitored in real time. the flags in the lvd register valid 20us after voltage detection is enabled. the hvd flag (bit 2 of the lvd register) is set only if v cc is lower than the v hvd . when voltage detection is enabled, the lvd flag also triggers irq5. the irq bit 5 latches the low voltage condition until it is cleared by instructions or reset. the irq5 interrupt is served if it is enabled in the imr register. otherwise, bit 5 of irq register is latched as a flag only. if it is necessary to receive an lvd interrupt upon power-up at an operating voltage lower than the low battery detect threshold, enable interrupts using the enable interrupt instruction (ei) prior to enabling the voltage detection. expanded register file control registers (0d) the expanded register file control registers (0d) are depicted in figure 36 through figure 40. note: note:
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0d) 59 figure 36. tc8 control register ((0d) 00h: read/write except where noted) ctr0 (0d) 00h d7 d6 d5 d4 d3 d2 d1 d0 0 p34 as port output * 1 timer8 output 0 disable t8 timeout interrupt** 1 enable t8 timeout interrupt 0 disable t8 data capture interrupt** 1 enable t8 data capture interrupt 00 sclk on t8** 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter timeout** r 1 t8 counter timeout occurred w 0 no effect w 1 reset flag to 0 0 modulo-n* 1 single pass r 0 t8 disabled * r 1 t8 enabled w0 stop t8 w 1 enable t8 * default setting after reset. ** default setting after reset. not reset with a stop mode recovery
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0d) 60 figure 37. t8 and t16 common control functions ((0d) 01h: read/write) ctr1 (0d) 01h d7 d6 d5 d4 d3 d2 d1 d0 transmit mode* r/w 0 t16_out is 0 initially* 1 t16_out is 1 initially capture mode r 0 no falling edge detection r 1 falling edge detection w 0 no effect w 1 reset flag to 0 transmit mode* r/w 0 t8_out is 0 initially* 1 t8_out is 1 initially capture mode r 0 no rising edge detection r 1 rising edge detection w 0 no effect w 1 reset flag to 0 transmit mode* 0 0 normal operation* 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 capture mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 11reserved transmit mode/t8/t16 logic 0 0 and** 01or 1 0 nor 1 1 nand capture mode 0 0 falling edge detection 01rising edge detection 1 0 both edge detection 11reserved transmit mode 0 p36 as port output * 1 p36 as t8/t16_out capture mode 0 p31 as demodulator input 1 p20 as demodulator input transmit/capture mode 0 transmit mode * 1 capture mode * default setting after reset. ** default setting after reset. not reset with a stop mode recovery.
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0d) 61 take care in differentiating the transmit mode from capture mode. depending on which of these two modes is operating, the ctr1 bit has different functions. changing from one mode to another cannot be performed without disabling the counter/timers. ctr2 (0d) 02h figure 38. t16 control register ((0d) 02h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 0 p35 is port output * 1 p35 is tc16 output 0 disable t16 timeout interrupt* 1 enable t16 timeout interrupt 0 disable t16 data capture interrupt** 1 enable t16 data capture interrupt 0 0 sclk on t16** 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 r 0 no t16 timeout** r 1 t16 timeout occurs w 0 no effect w 1 reset flag to 0 transmit mode 0 modulo-n for t16* 1 single pass for t16 capture mode 0 t16 recognizes edge 1 t16 does not recognize edge r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w1enable t16 * default setting after reset. ** default setting after reset. not reset with a stop mode recovery. notes:
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0d) 62 ctr3 (0d) 03h figure 39. t8/t16 control register (0d) 03h: read/write (except where noted) if sync mode is enabled, the first pulse of t8 (carrier) is always synchronized with t16 (demo dulated signal). it can always provide a full carrier pulse. d7 d6 d5 d4 d3 d2 d1 d0 reserved no effect when written always reads 11111 sync mode 0 disable sync mode** 1 enable sync mode t 8 enable r 0* t 8 disabled r 1 t 8 enabled w 0 stop t 8 w 1 enable t 8 t 16 enable r 0* t 16 disabled r 1 t 16 enabled w 0 stop t 16 w 1 enable t 16 * default setting after reset. ** default setting after re set. not reset after stop mode recovery note:
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0f) 63 lvd (0d) 0ch figure 40. voltage detection register expanded register file control registers (0f) the expanded register file control registers (0f) are depicted in figures 41 through figure 54. d7 d6 d5 d4 d3 d2 d1 d0 voltage detection 0: disable * 1: enable lvd flag (read only) 0: lvd flag reset * 1: lvd flag set hvd flag (read only) 0: hvd flag reset * 1: hvd flag set reserved (must be 0) * default setting after reset.
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0f) 64 pcon (0f) 00h figure 41. port configuration register (pcon) ((0f)00h: write only d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output * 1 p34, p37 comparator output reserved. (must be 1) port 0 0: open-drain 1: push-pull * reserved (must be 1) * default setting after reset
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0f) 65 smr (0f) 0bh figure 42. stop mode recovery register ((0f) 0bh: d6?d0=write only, d7=read only) d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * 1 on reserved (must be 0) stop-mode recovery source 000 por only* * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0?3 111 p2 nor 0?7 stop delay 0off 1 on * * * * stop recovery level * * * 0 low** 1 high stop flag 0 por * * * * * 1 stop recovery * * * default setting after reset * * set after stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source. not reset with a st op mode recovery. * * * * * default setting after power on reset
crimzon tm zlr16300 product specification ps021410-0605 expanded register file control registers (0f) 66 smr2 (0f) 0dh figure 43. stop mode recovery register 2 ((0f) 0dh: d2?d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low 1 high reserved (must be 0) note: if used in conjunction with sm r, either of the two specified ev ents causes a stop-mode recovery. * default setting after reset. not reset with a stop mode recovery. * * at the xor gate input
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 67 wdtmr (0f) 0fh figure 44. watch-dog timer register ((0f) 0fh: write only) standard control registers r246 p2m (f6h) figure 45. port 2 mode register (f6h: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01 20 ms min.* 10 40 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p27?p20 i/o definition 0 defines bit as output 1 defines bit as input * * default setting after reset. not reset with a stop mode recovery.
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 68 r247 p3m (f7h) figure 46. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 0: port 2 open drain * 1: port 2 push-pull 0= p31, p32 digital mode* 1= p31, p32 analog mode reserved (must be 0) * default setting after reset. not reset with a stop mode recovery.
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 69 r248 p01m (f8h) figure 47. port 0 register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p00?p03 mode 0: output 1: input * reserved (must be 0) reserved (must be 1) reserved (must be 0) p07?p04 mode 0: output 1: input * reserved (must be 0) * default setting after reset; only p00, p01 and p07 are available on 20-pin configurations.
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 70 r249 ipr (f9h) figure 48. interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b >c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq1, irq4, priority (group c) 0: irq1 > irq4 1: irq4 > irq1 irq0, irq2, priority (group b) 0: irq2 > irq0 1: irq0 > irq2 irq3, irq5, priority (group a) 0: irq5 > irq3 1: irq3 > irq5 reserved; must be 0
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 71 r250 irq (fah) figure 49. interrupt request register (fah: read/write) r251 imr (fbh) figure 50. interrupt mask register (fbh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 irq5 = lvd inter edge p31 p32 = 00 p31 p32 = 01 p31 p32 = 10 p31 p32 = 11 d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5?irq0 (d0 = irq0) reserved (must be 0) 0 master interrupt disable * 1 master interrupt enable * * * default setting after reset * * only by using ei, di inst ruction; di is required before changing the imr register
crimzon tm zlr16300 product specification ps021410-0605 standard control registers 72 r252 flags (fch) figure 51. flag register (fch: read/write) r253 rp (fdh) figure 52. register pointer (fdh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign tag zero flag carry flag d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer default setting after reset = 0000 0000
crimzon tm zlr16300 product specification ps021410-0605 package information 73 r254 sph (feh) figure 53. stack pointer high (feh: read/write) r255 spl (ffh) figure 54. stack pointer low (ffh: read/write) package information package information for all device versi ons of zgr16300 is depicted in figures 55 through figure 60. d7 d6 d5 d4 d3 d2 d1 d0 general-purpose register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer low byte (sp7?sp0)
crimzon tm zlr16300 product specification ps021410-0605 package information 74 figure 55. 20-pin dip package diagram figure 56. 20-pin soic package diagram
crimzon tm zlr16300 product specification ps021410-0605 package information 75 figure 57. 20-pin ssop package diagram
crimzon tm zlr16300 product specification ps021410-0605 package information 76 figure 58. 28-pin soic package diagram
crimzon tm zlr16300 product specification ps021410-0605 package information 77 figure 59. 28-pin dip package diagram
crimzon tm zlr16300 product specification ps021410-0605 ordering information 78 figure 60. 28-pin ssop package diagram please check with zilog ? on the actual bonding diagram and coordinate for chip-on-board assembly. ordering information the following table provides ordering information for the zlr16300 16k, 8k, 4k, 2k, and 1k parts. symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a' note:
crimzon tm zlr16300 product specification ps021410-0605 ordering information 79 memory size part no. description 16k zlr16300h2816c 28-pin ssop 16k rom zlr16300p2816c 28-pin pdip 16k rom zlr16300s2816c 28-pin soic 16k rom zlr16300h2016c 20-pin ssop 16k rom zlr16300p2016c 20-pin pdip 16k rom zlr16300s2016c 20-pin soic 16k rom 8k zlr16300h2808c 28-pin ssop 8k rom zlr16300p2808c 28-pin pdip 8k rom zlr16300s2808c 28-pin soic 8k rom zlr16300h2008c 20-pin ssop 8k rom zlr16300p2008c 20-pin pdip 8k rom zlr16300s2008c 20-pin soic 8k rom 4k zlr16300h2804c 28-pin ssop 4k rom zlr16300p2804c 28-pin pdip 4k rom zlr16300s2804c 28-pin soic 4k rom zlr16300h2004c 20-pin ssop 4k rom zlr16300p2004c 20-pin pdip 4k rom zlr16300s2004c 20-pin soic 4k rom 2k zlr16300h2802c 28-pin ssop 2k rom zlr16300p2802c 28-pin pdip 2k rom zlr16300s2802c 28-pin soic 2k rom zlr16300h2002c 20-pin ssop 2k rom zlr16300p2002c 20-pin pdip 2k rom zlr16300s2002c 20-pin soic 2k rom 1k zlr16300h2801c 28-pin ssop 1k rom zlr16300p2801c 28-pin pdip 1k rom zlr16300s2801c 28-pin soic 1k rom ZLR16300H2001C 20-pin ssop 1k rom zlr16300p2001c 20-pin pdip 1k rom zlr16300s2001c 20-pin soic 1k rom zlp32300100kit development system zlp323ice01zem emulator note: 1. replace c with g for lead-free packaging. 2. contact www.zilog.com for the die form.
crimzon tm zlr16300 product specification ps021410-0605 ordering information 80 for fast results, contact your local zilog sales office for assistance in ordering the part desired. codes zl = zilog low voltage family r = rom 16300 = family designation p = package type: h = ssop p = plastic dip s = soic ## = number of pins cc = memory size x = molding compound example zl r 16300 p 28 16 c molding compound memory size number of pins package type family designation rom zilog low voltage family
crimzon tm zlr16300 product specification ps021410-0605 index 81 index numerics 16-bit counter/timer circuits 39 20-pin dip package diagram 74 20-pin ssop package diagram 75 28-pin dip package diagram 77 28-pin soicpackage diagram 76 28-pin ssop package diagram 78 8-bit counter/timer circuits 35 a absolute maximum ratings 6 ac characteristics 10 timing diagram 10 address spaces, basic 2 architecture 2 expanded register file 21 b basic address spaces 2 block diagram, zlr16300 functional 3 c capacitance 8 capture_int_mask 27 , 32 characteristics ac 10 dc 8 clock 46 comparator inputs/outputs 18 configuration port 0 13 port 2 14 port 3 15 port 3 counter/timer 17 counter/timer 16-bit circuits 39 8-bit circuits 35 brown-out voltage/standby 57 clock 46 demodulation mode count capture flow- chart 37 demodulation mode flowchart 38 eprom selectable options 57 glitch filter circuitry 33 halt instruction 47 input circuit 33 interrupt block diagram 44 interrupt types, sources and vectors 45 oscillator configuration 46 output circuit 42 ping-pong mode 41 port configuration register 48 resets and wdt 56 sclk circuit 51 stop instruction 47 stop mode recovery register 50 stop mode recovery register 2 54 stop mode recovery source 52 t16 demodulation mode 40 t16 transmit mode 39 t16_out in modulo-n mode 40 t16_out in single-pass mode 40 t8 demodulation mode 36 t8 transmit mode 33 t8_out in modulo-n mode 36 t8_out in single-pass mode 36 transmit mode flowchart 34 voltage detection and flags 58 watch-dog timer mode register 55 watch-dog timer time select 56 counter/timer functional blocks input circuit 33 t8 transmit mode 33 counter_int_mask 32 crt3 t8/t16 control register register 32
crimzon tm zlr16300 product specification ps021410-0605 index 82 ctr(d)01h t8 and t16 common functions 28 ctr1 (0d)01 27 ctr3 t8/t16 control ctr3(0d)03h 32 d dc characteristics 8 demodulation mode count capture flowchart 37 flowchart 38 t16 40 t8 36 description functional 18 general 2 pin 5 e eprom selectable options 57 expanded register file 20 expanded register file architecture 21 expanded register file control registers 63 flag 72 interrupt mask register 71 interrupt priority register 70 interrupt request register 71 port 0 and 1 mode register 69 port 2 configuration register 67 port 3 mode register 68 port configuration register 67 register pointer 72 stack pointer high register 73 stack pointer low register 73 stop-mode recovery register 65 stop-mode recovery register 2 66 t16 control register 61 t8 and t16 common control functions reg- ister 60 tc8 control register 58 watch-dog timer register 67 f features standby modes 1 zlr16300 1 functional description counter/timer functional blocks 33 ctr0(0d)00h register 26 ctr1(0d)01h register 28 ctr2(0d)02h register 30 expanded register file 20 expanded register file architecture 21 hi16(0d)09h register 25 hi8(0d)0bh register 25 l08(0d)0ah register 25 l0i6(0d)08h register 25 program memory map 19 ram 18 register description 57 register file 23 register pointer 22 register pointer detail 24 stack 24 tc16h(0d)07h register 25 tc16l(0d)06h register 26 tc8h(0d)05h register 26 tc8l(0d)04h register 26 tc8l(d)04h register 26 g glitch filter circuitry 33 h halt instruction, counter/timer 47 i input circuit 33 interrupt block diagram, counter/timer 44 interrupt types, sources and vectors 45
crimzon tm zlr16300 product specification ps021410-0605 index 83 l low-voltage detection register 57 m memory, program 18 modulo-n mode t16_out 40 t8_out 36 o oscillator configuration 46 output circuit, counter/timer 42 p p34_out 27 p35_out 32 p36_out/demodulator input 29 package information 20-pin dip package diagram 74 20-pin ssop package diagram 75 28-pin dip package diagram 77 28-pin soic package diagram 76 28-pin ssop package diagram 78 pin configuration 20-pin dip/soic/ssop 5 28-pin dip/soic/ssop 6 pin functions port 0 (p07 - p00) 12 port 0 configuration 13 port 2 (p27 - p20) 13 port 2 (p37 - p30) 14 port 2 configuration 14 port 3 configuration 15 port 3 counter/timer configuration 17 xtal1 (time-based input 12 xtal2 (time-based output) 12 ping-pong mode 41 port 0 configuration 13 pin function 12 port 2 configuration 14 pin function 13 port 3 configuration 15 counter/timer configuration 17 port 3 pin function 14 port configuration register 48 power connections 2 power supply 5 program memory 18 map 19 r ratings, absolute maximum 6 register 54 ctr0(0d)00h 26 ctr1 (0d) 01 27 ctr1(0d)01h 28 ctr2(0d)02h 30 flag 72 hi16(0d)09h 25 hi8(0d)0bh 25 interrupt priority 70 interrupt request 71 interruptmask 71 l016(0d)08h 25 l08(0d)0ah 25 lvd(d)0ch 57 pointer 72 port 0 and 1 69 port 2 configuration 67 port 3 mode 68 port configuration 48 , 67 stack pointer high 73 stack pointer low 73 stop mode recovery 50 stop mode recovery 2 54 stop-mode recovery 65 stop-mode recovery 2 66 t16 control 61 t8 and t16 common control functions 60 tc16h(0d)07h 25
crimzon tm zlr16300 product specification ps021410-0605 index 84 tc16l(0d)06h 26 tc8 control 58 tc8h(0d)05h 26 tc8l(0d)04h 26 tc8l(d)04h 26 voltage detection 63 watch-dog timer 67 register description counter/timer2 ls-byte hold 26 counter/timer2 ms-byte hold 25 counter/timer8 control 26 counter/timer8 high hold 26 counter/timer8 low hold 26 ctr2 counter/timer 16 control 30 t16_capture_lo 25 t8 and t16 common functions 28 t8_capture_hi 25 t8_capture_lo 25 register file 23 expanded 20 register pointer 22 detail 24 resets and wdt 56 s sclk circuit 51 single/modulo-n 27 , 31 single-pass mode t16_out 40 t8_out 36 stack 24 standard test conditions 7 standby modes 1 stop instruction, counter/timer 47 stop mode recovery 2 register 54 source 52 stop mode recovery 2 54 stop mode recovery register 50 t t 16 clock 32 t16 enable 31 t16 initial out/falling edge 30 t16 transmit mode 39 t16_capture_hi 25 t8 and t16 common functions 27 t8 clock 27 t8 enable 27 t8 intiial out/rising edge 30 t8 transmit mode 33 t8/t16_logic/edge_detect 30 t8_capture_hi 25 test conditions, standard 7 test load diagram 7 time_out 32 timeout 27 timers counter/timer2 ls-byte hold 26 counter/timer2 ms-byte hold 25 counter/timer8 high hold 26 counter/timer8 low hold 26 ctr0 counter/timer8 control 26 t16_capture_hi 25 t16_capture_lo 25 t8_capture_hi 25 t8_capture_lo 25 timing diagram, ac 10 transmit mode flowchart 34 transmit_submode/glitch filter 30 v vcc 5 voltage brown-out/standby 57 detection and flags 58 voltage detection register 63
crimzon tm zlr16300 product specification ps021410-0605 index 85 w watch-dog timer mode registerwatch-dog timer mode regis- ter 55 time select 56 x xtal1 5 xtal1 pin function 12 xtal2 5 xtal2 pin function 12 z zlr16300 family members 1

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